The present invention relates to the field of CMOS logical circuits manufactured in partially depleted silicon-on-insulator technology (PD-SOI: Partially Depleted Silicon-on-Insulator), and more particularly, to the evaluation or characterization of these circuits, in terms of time delay, for example.
In recent years SOI technology (Silicon On Insulator) has proven to be a particularly interesting alternative to classic CMOS technology carried out on solid silicon. More particularly, the so-called effects of xe2x80x9cfloating substratexe2x80x9d, well known to the skilled artisan, and the reduction in joining capacities are the main causes of improved performances contributed by this SOI technology. On the contrary, the floating substrate does have disadvantages.
One such disadvantage is the effect of hysteresis of the threshold voltage of a transistor, which is translated by variations in time delay, that is, variations in the propagation time of a signal between the input and the output of a logical cell incorporating such transistors, for example an inverter. Partially depleted silicon-on-insulator technology introduces a xe2x80x9ctimexe2x80x9d dependence of delays, such that the same structure can have different delays from cycle to cycle when it is rated by a clock signal. A method for initializing the voltage of the floating substrate is generally used in the design of SOI circuits and error tolerances are utilized to take these time constraints into account. However, such an approach can lead to overestimating or underestimating the performance of the structure.
Furthermore, not only delays in worst-case scenarios but also delays in best-case scenarios must be known, especially for problems of synchronization into account. However, both the worst cases and the best cases are difficult to identify since the parameters of design process such as current gain, input slope, charge, feed and temperature, play a key role. And, the variable nature of the threshold voltages in PD-SOI technologies is such that propagation of a given transition between the input and output of a logical cell leads to a different delay according to what is found in static balance conditions (DC) or else if a state of dynamic equilibrium (AC xe2x80x9csteady statexe2x80x9d) has been attained. And, it may prove impossible in practice to characterize a logical cell by exhaustive simulations since several thousand cycles, thus several hours of simulation, are necessary to reach dynamic equilibrium even for simple inverter-type cells. The characterization of a much more complex cell cannot be done with such an approach.
An object of the invention is to provide a method and device for rapid evaluation of time delays of a logic cell in the dynamic equilibrium state, as well as rapid evaluation of delays in best-case and worst-case scenarios, even for complex cells.
The invention therefore provides a process for evaluating/characterizing a logical CMOS cell to be produced in partially depleted silicon-on-insulator technology. This process comprises modeling the cell, for example by using a transistor model of type BSIM3SOI, and a phase for determining internal potentials (or potentials of floating substrates) of the transistors of the cell. This determination phase is based on operational simulation of the modeled cell utilizing a binary stimulation signal. In this determination phase, the floating substrate of each transistor and the cell, and at predetermined successive instants of injection, is injected with a charge proportional to the variation of the internal potential of this transistor, a variation determined during a predetermined time interval of the stimulation signal preceding the current instant of injection and exempt from injection, so as to accelerate the charge or the discharge of the floating substrate of the transistor. The charge is injected for example by injecting a current. Of course, the injected charge can be positive or negative, allowing the floating substrate of a transistor to be discharged or charged.
According to an embodiment of the invention, the injection current is determined such that, after injection, the variation in internal potential of the transistor in question reaches n times the measured variation of the internal potential. The value of n is determined for example from measuring the variation of the internal potential of a transistor of the cell, for example during a first cycle of the stimulation signal, and from the estimated amplitude of the variation of the internal potential of this transistor between its state of static equilibrium and its state of dynamic equilibrium.
According to an embodiment of the invention, in which the stimulation signal comprises a transition separating two plateaus in each period, an injection instant is generally found at a point where the internal potential of the transistor is relatively stable. By way of example, an injection instant can be located during a plateau and at a transition distance. The injection duration of the current is then advantageously selected greater than the time pitch of the operational simulation and less than the duration of a plateau.
According to an embodiment of the invention, two consecutive injection instants can be spaced by a duration equal to two periods of the stimulation signal. The time interval then has a duration equal to a period of the stimulation signal. In such a variation, the cell thus sees the equivalent of 1+n impulses of the stimulation signal over the course of two simulation periods, resulting in an acceleration factor equal to (1+n)/2.
To ensure that the predetermined time interval, during which the variation of the internal potential of the transistor will be calculated, is exempt from injection, an instant which precedes the injection instant of 1.5 periods of the stimulation signal can be taken as the initial instant of the time interval. In addition, the final instant of this time interval can be taken as being the instant preceding the injection instant of 0.5 period of the stimulation signal.
According to an embodiment of the invention, for operational simulation, each transistor of the cell is replaced by a model of this transistor linked to three modeled voltage-controlled voltage sources, enabling determination of an internal potential target of the transistor to be reached after injection. Also, the transistor is likewise linked to a modeled current source supplying the injection current proportional to the difference between the internal potential target and the internal potential at the injection instant.
Thus, for example, the first source of voltage supplied at the injection instant, the value of the internal potential of the transistor delayed by a period of the stimulation signal. The second source of voltage supplies the variation of internal potential over a period, delayed by a half-period of the stimulation signal. And the third source voltage supplies the internal potential target.
The invention thus determines, for example, evolution of the internal potentials of the transistors of the cell but also the evolution of the time delays, or again evolution of other characterization parameters such as consumption or fault current, from the state of static equilibrium to the dynamic equilibrium state, relative to the rising and falling transitions of the stimulation signal, and for the two initial values of the stimulation signal. From this can be deduced the worst cases or the best cases for these parameters. This direct determination, in particular of the worst cases of time delays, constitutes a considerable advantage of the method.
An object of the invention is also a device for characterizing a CMOS logical cell being created in a partially depleted silicon-on-insulator technology. This device includes means/unit for modeling the cell and processing means/unit suitable for effecting a determination phase of the internal potentials of the cell based on operational simulation of the modeled cell utilizing a periodic binary stimulation signal. In this determination phase the processing means are suitable for injecting into the floating substrate of each transistor of the cell, and at predetermined successive injection instants, a charge proportional to the variation of the internal potential of this transistor determined during a predetermined time interval of a stimulation signal preceding the current injection instant and exempt from injection, to accelerate the charge or discharge of the floating substrate of a transistor.
According to an embodiment of the invention, the processing means determine the injection current such that after injection the variation in internal potential of the transistor in question reaches n times the measured variation of the internal potential. According to an embodiment of the invention, the processing means determine the value of n from measuring the variation of the internal potential of a transistor of the cell and an estimated amplitude of the variation of the internal potential of this transistor between its state of static equilibrium and its state of dynamic equilibrium.
According to an embodiment of the invention, the modeling means comprise for each transistor of the cell a model of this transistor linked to three modeled sources of voltage controlled in voltage, allowing an internal potential target of the transistor to be reached after injection to be determined, and to a modeled source of current supplying the injection current proportional to the difference between the internal potential target and the internal potential at the instant of injection.
The processing means are also advantageously suitable for determining the evolution of the internal potentials of the transistors of the cell from the static equilibrium state to the dynamic equilibrium state, relative to the rising and falling transitions of the stimulation signal and for the two initial values of the stimulation signal, and are suitable for deducing the internal potentials of the transistors corresponding to the worst case or best case of the time delay of the cell.
The processing means can also be suitable for determining the evolution of the different time delays of the cell, and for determining the time delay corresponding to the worst case or the best case. The processing means can also be suitable for determining the evolution of other characterization parameters of the cell.